Semiconductor device and method of manufacturing semiconductor device

ABSTRACT

According to one embodiment, at first, a compound semiconductor layer is bonded to a position straddling a plurality of chip formation regions arranged on a substrate. One of the chip formation regions has a first size, and the compound semiconductor layer has a second size smaller than the first size. Thereafter, the compound semiconductor layer is processed to provide compound semiconductor elements on the chip formation regions. Then, the substrate is divided to correspond to the chip formation regions.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is a divisional application of U.S. application Ser.No. 15/257,433, filed on Sep. 6, 2016, which is based upon and claimsthe benefit of priority from Japanese Patent Application No.2016-050211, filed on Mar. 14, 2016; the entire contents of which areincorporated herein by reference.

FIELD

Embodiments described herein relate generally to a semiconductor deviceand a method of manufacturing a semiconductor device.

BACKGROUND

Research and development have been actively performed for a techniquecalled “Silicon Photonics”, in which optical elements, such as lightemitting/light receiving elements, a waveguide, and a demultiplexer, areformed on a silicon chip equipped with a CMOS (ComplementaryMetal-Oxide-Semiconductor) circuit or the like. Particularly, such aform that a laser light source and so forth made of a group III-Vcompound semiconductor material are integrated on silicon (which will bereferred to as “III-V/Si”, hereinafter) can become an importanttechnique, depending on the future development of Silicon Photonics.Further, as other applications of the III-V/Si, there can be consideredan application to a ultra high speed electronics field in which a ultrahigh speed transistor made of a group III-V compound semiconductor iscombined with a silicon CMOS, and an application to a structure in whicha sensor and an actuator formed as group III-V compound semiconductordevices are integrated on a signal processing circuit made of silicon.

BRIEF DESCRIPTION OF THE DRAWINGS

FIGS. 1A and 1B are views schematically showing a structural example ofa semiconductor device according to a first embodiment;

FIGS. 2A to 2H are sectional views showing an example of the sequence ofa method of manufacturing a semiconductor device according to the firstembodiment;

FIGS. 3A and 3B are top views showing the example of the sequence of amethod of manufacturing a semiconductor device according to the firstembodiment;

FIGS. 4A and 4B are top views showing another example of the placementof compound semiconductor chips according to the first embodiment;

FIGS. 5A and 5B are top views showing another example of the placementof compound semiconductor chips according to the first embodiment;

FIGS. 6A and 6B are top views showing another example of the placementof compound semiconductor chips according to the first embodiment;

FIGS. 7A and 7B are views schematically showing a structural example ofa semiconductor device according to a second embodiment; and

FIGS. 8A and 8B are top views showing part of the sequence of a methodof manufacturing a semiconductor device according to the secondembodiment.

DETAILED DESCRIPTION

In general, according to one embodiment, at first, a compoundsemiconductor layer is bonded to a position straddling a plurality ofchip formation regions arranged on a substrate. One of the chipformation regions has a first size, and the compound semiconductor layerhas a second size smaller than the first size. Thereafter, the compoundsemiconductor layer is processed to provide compound semiconductorelements on the chip formation regions. Then, the substrate is dividedto correspond to the chip formation regions.

Conventionally, for example, the III-V/Si is manufactured as follows. Atfirst, CMOS circuits or the like are respectively formed in chipformation regions each having a first size on a silicon substrate.Thereafter, group III-V compound semiconductor chips diced in a secondsize smaller than the first size are respectively transferred onto chipformation regions on the silicon substrate. Thereafter, the group III-Vcompound semiconductor chips are processed on the silicon substrate, andthereby the device is formed. As a final step, the silicon substrate isdiced in the first size, so that a group III-V compound semiconductordevice is obtained in a state formed on a silicon chip having the firstsize.

However, in the conventional technique described above, there is aproblem in which, if the size of the necessary device made of a groupIII-V compound semiconductor material, i.e., the group III-V compoundsemiconductor chip, is formed smaller, it becomes difficult to bond thechip to each of the chip formation regions on the silicon substrate.

Exemplary embodiments of a semiconductor device and a method ofmanufacturing a semiconductor device will be explained below in detailwith reference to the accompanying drawings. The present invention isnot limited to the following embodiments. The sectional views of asemiconductor device used in the following embodiments are schematic,and so the relationship between the thickness and width of each layerand/or the thickness ratios between respective layers may be differentfrom actual states. Further, the size of each chip described below is amere example and is not limiting.

First Embodiment

FIGS. 1A and 1B are views schematically showing a structural example ofa semiconductor device according to a first embodiment. FIG. 1A is a topview, and FIG. 1B is a sectional view taken along a line A-A of FIG. 1A.This semiconductor device formed of a semiconductor chip 10 has aconfiguration in which a first structure 20, optical function elements30, and second structures 40 are arranged on a substrate 11 having asquare shape.

As the substrate 11, a silicon substrate or SOI (Silicon-On-Insulator)substrate may be used. If such a substrate, particularly the SOIsubstrate, is used, it becomes easier to fabricate not only an electriccircuit formed of, e.g., a transistor and wiring lines, but also anoptical function element, such as a waveguide, on the substrate 11.

The first structure 20 includes function blocks composed of circuitelements, optical function elements, or wiring structures connected tothese elements, which are arranged on the substrate 11 or in thesubstrate 11, and the upper surface of the first structure 20 is in aplanarized state. The circuit element may be exemplified by a CMOScircuit or the like. The optical function element may be exemplified bya waveguide or the like. Each of the circuit element and the opticalfunction element is made of a semiconductor material, such as silicon, aconductive material, such as copper or aluminum, and an insulatormaterial, such as a silicon oxide film or silicon nitride film.

The function block is formed of an element pattern which is composed ofa circuit element or optical function element and a wiring structure sothat the element pattern can have a predetermined function. In theexample shown in FIG. 1A, the function blocks arranged here are a CPU(Central Processing Unit) 201, a GPGPU (General-Purpose computing onGraphics Processing Units) 202, a memory 203, a PLD (Programmable LogicDevice) 204, a peripheral logic circuit 205, a SerDes(Serializer/Deserializer) 206, a reception light/electric signalconversion circuit 207, and an electric signal/transmission lightconversion circuit 208.

In the first structure 20, there is a case where various device elementsand wiring structures having different heights are arranged and so theupper surface of the first structure 20 has different levels dependingon the position. In this case, the upper surface is planarized by aplanarization film (not shown). As the planarization film, a siliconoxide film or the like may be used. The upper surface of the firststructure 20 is preferably has a root mean square roughness (which willbe referred to as “RMS”, hereinafter) of 0 nm or more and 3 nm or less.If the RMS is larger 3 nm, the bonding of the optical function element30 onto the upper surface, which will be described later with referenceto a manufacturing method, may become unable to be performed in a goodstate. The planarized upper surface of the first structure 20 is made ofsilicon or silicon oxide. On the upper surface of the first structure20, different materials may be exposed, depending on the position.Further, a material exposed on the upper surface of the first structure20 may be different from a material present under the exposed material.

The optical function element 30 may be exemplified by a light receivingelement 31 or light emitting element 32. The light receiving element 31is bonded on the reception light/electric signal conversion circuit 207.The light emitting element 32 is formed on the electricsignal/transmission light conversion circuit 208. As the light emittingelement 32, for example, a laser diode may be used. The optical functionelement 30 is made of a group III-V compound semiconductor, such as InP,GaAs, GaP, or InAs. The optical function element 30 is bonded onto thefirst structure 20 by means of oxide film bonding or adhesive bonding.

The second structure 40 is a structure arranged on the first structure20 provided with the optical function element 30. For example, thesecond structure 40 is a wiring structure that connects the opticalfunction element 30 to another device element built in the firststructure 20.

When the semiconductor chip 10 is in operation, each of the CPU 201 andthe GPGPU 202 shows a heat release value far larger than the otherfunction blocks. On the other hand, the optical function element 30 canbe easily affected by heat. Accordingly, the optical function element 30is preferably arranged at a position distant as possible from a functionblock having a large heat release value so that the optical functionelement 30 will be less affected by the thermal influence of thefunction block having a large heat release value.

In consideration of the matter described above, according to the firstembodiment, the optical function element 30 is arranged near a corner ofthe substrate 11 having a square shape. The arrangement position of theoptical function element 30 is preferably set at a position most distantfrom the center of the substrate 11. Alternatively, the optical functionelement 30 is arranged such that no function block is present in aregion opposite to that side where the function block having a largeheat release value is arranged with respect to the arrangement positionof the optical function element 30, i.e., in a region outside thearrangement position of the optical function element 30. However, adevice element, such as a wiring line, which does not have a specialfunction may be arranged in a region between the arrangement position ofthe optical function element 30 and an end portion of the substrate 11closest to the arrangement position of the optical function element 30.

The arrangement position of the optical function element 30 is set asdescribed above, and thereby the optical function element 30 can be lessaffected by the thermal influence of a circuit element having a largeheat release value.

It should be noted that FIG. 1A illustrates the light receiving element31 and the light emitting element 32 as examples of the optical functionelement 30, but a modulator, demultiplexer, or waveguide may be providedas the optical function element 30.

Next, an explanation will be given of a method of manufacturing asemiconductor device of this type. FIGS. 2A to 2H are sectional viewsshowing an example of the sequence of a method of manufacturing asemiconductor device according to the first embodiment. FIGS. 3A and 3Bare top views showing the example of the sequence of a method ofmanufacturing a semiconductor device according to the first embodiment.

At first, as shown in FIGS. 2A and 3A, first structures 20 respectivelyhaving predetermined element patterns are formed over respective chipformation regions 10R of a substrate 11, such as a silicon substrate,and the upper surfaces of the first structures 20 are planarized. Theelement patterns may be exemplified by a circuit element, such as a CMOScircuit, an optical function element, such as a waveguide, and a wiringline connected to the circuit element or optical function element.Further, the length of one side of each of the chip formation regions10R is set to 3 mm.

The element patterns are formed by use of ordinary semiconductormanufacturing processes. For example, a processing object film (notshown) for constituting the element patterns is formed on the substrate11 by use of a film formation method, such as a CVD (Chemical VaporDeposition) method or PVD (Physical Vapor Deposition) method.Thereafter, a resist (not shown) is applied onto the processing objectfilm, and resist patterns for forming the element patterns are formed byuse of a lithography technique. At this time, the square chip formationregions 10R to be chips later are formed on the substrate 11, and theresist patterns are respectively formed in the chip formation regions10R. In the first embodiment, the resist patterns are formed such thatfour chip formation regions 10R sharing one corner part are treated asone chip sharing unit 15 and this chip sharing unit 15 is repeatedlyarranged in a two-dimensional state as shown in FIG. 3A.

In the single chip sharing unit 15, the chip formation regions 10R arearranged to be four-fold rotational symmetric. Specifically, the resistpattern arrangements of the respective chip formation regions 10Rrotated by 90° about the center of the chip sharing unit 15 overlap withthe resist pattern arrangements of the respective chip formation regions10R not rotated.

As shown in FIG. 3A, an X-axis and a Y-axis are defined on the substrate11. It is assumed that, in the single chip sharing unit 15, the regionarranged on the X-axis negative side and the Y-axis positive side is afirst chip formation region 10R-1, the region arranged on the X-axispositive side and the Y-axis positive side is a second chip formationregion 10R-2, the region arranged on the X-axis positive side and theY-axis negative side is a third chip formation region 10R-3, and theregion arranged on the X-axis negative side and the Y-axis negative sideis a fourth chip formation region 10R-4. On this assumption, the resistpattern formed in the first chip formation region 10R-1 is the same asthat of the fourth chip formation region 10R-4 rotated clockwise by 90°,the resist pattern formed in the second chip formation region 10R-2 isthe same as that of the first chip formation region 10R-1 rotatedclockwise by 90°, the resist pattern formed in the third chip formationregion 10R-3 is the same as that of the second chip formation region10R-2 rotated clockwise by 90°, and the resist pattern formed in thefourth chip formation region 10R-4 is the same as that of the third chipformation region 10R-3 rotated clockwise by 90°.

In order to form the resist patterns in a layer of these chip formationregions 10R, a mask (reticle) of only one type is required. In thiscase, when a light exposure process is performed, at least one of themask and the substrate 11 is rotated so that the resist pattern of eachof the chip formation regions 10R can be formed. Alternatively, masks offour types may be prepared such that they have patterns the same inshape and different in orientation by 90°, or a mask of one type may beprepared such that it can be used to perform light exposure to theentire single chip sharing unit 15 at a time.

Thereafter, steps, such as film formation and etching, are repeated, sothat the element patterns are formed in the respective chip formationregions 10R. Then, a planarization film is formed on the substrate 11including the element patterns, and the uppermost surface of thesubstrate 11, i.e., the upper surface of the planarization film, isplanarized, by use of a CMP (Chemical Mechanical Polishing) method.Consequently, the first structures 20 are formed. At this time, theplanarization may be performed to expose the upper surfaces of part ofthe element patterns, or to cover the entirety of the element patternswith the planarization film. Here, the planarization only needs to setthe upper surfaces of the first structures 20 to have an RMS of 3 nm orless. As the planarization film, for example, a silicon oxide film maybe used.

On the other hand, in addition to the formation of the element patternsonto the substrate 11 shown in FIG. 2A; as shown in FIG. 2B, a groupIII-V compound semiconductor layer (which will be referred to as“compound semiconductor layer”, hereinafter) 37 is formed by use ofepitaxial growth over respective chip formation regions of a group III-Vcompound semiconductor substrate (which will be referred to as “compoundsemiconductor substrate”, hereinafter) 35. As the compound semiconductorsubstrate 35 and the compound semiconductor layer 37, InP, GaAs, GaP, orInAs may be used. The type and thickness of a film for forming thecompound semiconductor layer 37 may be changed, depending on the opticalfunction element 30 to be processed later. For example, in a case wherea light emitting element is to be formed, the compound semiconductorlayer 37 may be used in a state having a structure in which a quantumwell layer is sandwiched by clad layers formed on its upper and lowersurfaces.

Then, as shown in FIG. 2C, the compound semiconductor substrate 35formed with the compound semiconductor layer 37 is diced along dicinglines, and thereby it is divided into a plurality of compoundsemiconductor chips 36. Each of the compound semiconductor chips 36 hasa size of 1 mm square, for example.

Thereafter, as shown in FIGS. 2D and 3B, the compound semiconductorchips 36 are placed such that their surfaces each including the compoundsemiconductor layer 37 formed thereon face the first structures 20 onthe substrate 11. Here, each of the compound semiconductor chips 36 ispositioned such that its center is aligned with the center of each ofthe chip sharing units 15 of the substrate 11, and then the compoundsemiconductor chips 36 and the first structures 20 are bonded.Consequently, each of the compound semiconductor chips 36 is placed atthe corner part shared by the four chip formation regions 10Rconstituting each of the chip sharing units 15.

As the bonding of the compound semiconductor chips 36 to the firststructures 20, adhesive bonding or oxide film bonding may be used. Inthe case of the adhesive bonding, the compound semiconductor chips 36and the first structures 20 are bonded to each other via a resin, suchas BCB (Benzocyclobutene).

In the case of the oxide film bonding, the compound semiconductor chips36 and the first structures 20 are bonded to each other by use of ahydroxyl group formed on their surfaces. More specifically, the uppersurfaces of the first structures 20 and the surfaces of the compoundsemiconductor chips 36 each including the compound semiconductor layer37 formed thereon are terminated with a hydroxyl group. For example, theupper surfaces of the first structures 20 and the upper surfaces of thecompound semiconductor layers 37 are irradiated with plasma, and therebythe respective surfaces are activated.

Consequently, contaminants, such as organic matters, deposited on therespective surfaces are removed, and the surfaces are terminated with ahydroxyl group. Here, water molecules can be easily coupled by hydrogenbonds with the surfaces terminated with the hydroxyl group.

Then, the activated surfaces of the compound semiconductor chips 36 arebrought into close contact with the activated upper surfaces of thefirst structures 20. Consequently, the compound semiconductor chips 36are temporarily bonded to the first structures 20. At this time, betweenthe activated surfaces of the compound semiconductor chips 36 and theactivated surfaces of the first structures 20, water molecules coupledwith the hydroxyl group are connected to each other, and thereby theactivated surfaces are temporarily bonded to each other.

Thereafter, a pressure is physically applied to at least one of the rearside of the compound semiconductor chips 36 and the rear side of thesubstrate 11, and, in this state, they are heated to a temperature ofabout 200° C., for example. Consequently, the water molecules areremoved from the interface of bonding between the first structures 20and the compound semiconductor layers 37, and thereby the bonding isturned into covalent bonding formed by oxygen atoms, which is finalbonding originally aimed. In this respect, silicon and group III-Vcompound semiconductor have different thermal expansion coefficients.Accordingly, if the heating temperature is set higher than 250° C., aresidual thermal stress may be generated by a thermal effect after thebonding process ends, and/or a damage may be caused to the structureinside the compound semiconductor layer. In order to suppress theseproblems, the heating temperature is preferably set to 250° C. or less.

Further, as a method of bonding the compound semiconductor chips 36 tothe first structures 20, there is a pick and place method or a method ofusing an adhesive sheet. In the case of the pick and place method, eachof the compound semiconductor chips 36 is held by a flip chip bonder andplaced at the center of each of the chip sharing units 15 of thesubstrate 11.

In the case of the method of using the adhesive sheet, at first, theadhesive sheet (dicing tape) is stuck to the rear side of the compoundsemiconductor substrate 35 before the dicing shown in FIG. 2C, and thenthe compound semiconductor substrate 35 is diced into a plurality ofcompound semiconductor chips 36 without cutting the adhesive sheet.Thereafter, the adhesive sheet is stretched and expanded toward theperiphery. Consequently, the gap between adjacent compound semiconductorchips 36 is made wider. At this time, the distance between the centersof adjacent compound semiconductor chips 36 is set to be equal to thedistance between the centers of adjacent chip sharing units 15 of thesubstrate 11. Thereafter, the plurality of compound semiconductor chips36, which are stuck on the adhesive sheet, are positioned with respectto the substrate 11, and then the plurality of compound semiconductorchips 36 on the adhesive sheet are bonded to the first structures 20.

Then, as shown in FIG. 2E, the compound semiconductor substrate 35 isremoved from the compound semiconductor chips 36. As the removingmethod, mechanical grinding, dry etching, wet etching, or a method ofusing a combination of them may be selected. Consequently, only thecompound semiconductor layers 37 are left on the first structures 20.Further, the compound semiconductor layers 37 are processed by use of alithography technique and an etching technique, and thereby opticalfunction elements 30, such as a light emitting element and/or a lightreceiving element, are respectively formed in the chip formation regions10R that constitute each of the single chip sharing units 15. Each ofthe optical function elements 30 formed at this time has a size of 0.5mm square or less. For example, if the optical function element 30 is tobe utilized for a laser light source, a size of about 0.3 to 0.5 mm isenough to oscillate laser.

Thereafter, as shown in FIG. 2F, second structures 40 are formed on thesubstrate 11 formed with the optical function elements 30. For example,the second structure 40 may be exemplified by an electrode layer thatconnects an optical function element 30 to a device element of thecorresponding first structure 20 and an interlayer insulating film thatcovers the electrode layer.

Then, as shown in FIG. 2G, grooves 51 for demarcating the firststructures 20 respectively into the chip formation regions 10R areformed by use of a lithography technique and an etching technique. Then,as shown in FIG. 2H, the substrate 11 is diced along dicing lines.Consequently, semiconductor chips 10 are separated. Thus, each of thesemiconductor chips 10 is obtained together with an optical functionelement 30 bonded thereto, and so the process of manufacturing asemiconductor device ends.

In the explanation described above, FIGS. 2D and 3B show an example inwhich each of the compound semiconductor chips 36 is bonded to a regionincluding the center of the chip sharing unit 15 composed of four chipformation regions 10R, but this embodiment is not limited to thisexample. Further, in the explanation described above, the compoundsemiconductor substrate 35 including the epitaxial growth compoundsemiconductor layer 37 is divided into chips, and the chips eachincluding the compound semiconductor layer 37 are bonded to thesubstrate 11 made of silicon or the like, but this embodiment is notlimited to this example. For example, this embodiment covers a casewhere, after the compound semiconductor layer 37 is formed by use ofepitaxial growth on the compound semiconductor substrate 35, only apartly diced compound semiconductor layer 37 is picked up therefrom bylifting off a separation object portion by use of laser or chemicalsolvent, and then this compound semiconductor layer 37 is bonded to thesubstrate 11 made of silicon or the like.

FIGS. 4A to 6B are top views showing other examples of the placement ofcompound semiconductor chips according to the first embodiment. FIGS.4A, 5A, and 6A are top view schematically showing examples of thepositions of optical function elements in one semiconductor chip, andFIGS. 4B, 5B, and 6B are top view schematically showing examples of theplacement state of compound semiconductor chips on chip formationregions of a substrate.

In the example shown in FIG. 4A, a light receiving element 31, which isa first optical function element, is arranged at one corner of asemiconductor chip 10. Further, a light emitting element 32, which is asecond optical function element, is arranged at a corner opposite to thecorner at which the light receiving element 31 is arranged.

FIG. 4B shows an example of a method of placing compound semiconductorchips 36 to manufacture the semiconductor chip 10 shown in FIG. 4A. Asshown in FIG. 4B, in a single chip sharing unit 15, compoundsemiconductor chips 36 are respectively placed at the four corners and aregion including the center. Consequently, one compound semiconductorchip 36 is shared by the four chip formation regions 10R adjacent toeach other. In this case, the single chip sharing unit 15 has afour-fold rotational symmetric relation relative to its center. Here,each of the compound semiconductor chips 36 placed at the corners of thechip sharing unit 15 will be processed into light receiving elements 31,and the compound semiconductor chip 36 placed at the region includingthe center will be processed into light emitting elements 32.

In the example shown in FIG. 5A, semiconductor chips 10 a to 10 d offour types are included in a semiconductor chip 10. Here, thearrangement direction of a certain element pattern is used as areference, and the upper left corner, upper right corner, lower rightcorner, and lower left corner of the semiconductor chip 10 will bereferred to as a first corner, second corner, third corner, and fourthcorner, respectively. In the semiconductor chip 10 a, a light receivingelement 31, which is a first optical function element, is arranged atthe fourth corner, a light emitting element 32, which is a secondoptical function element, is arranged at the third corner, and a radiofrequency (RF) device element 33, which is a third optical functionelement, is arranged at the first corner. In the semiconductor chip 10b, the light receiving element 31 is arranged at the third corner, thelight emitting element 32 is arranged at the fourth corner, and the RFdevice element 33 is arranged at the second corner. In the semiconductorchip 10 c, the light receiving element 31 is arranged at the secondcorner, the light emitting element 32 is arranged at the first corner,and the RF device element 33 is arranged at the third corner. In thesemiconductor chip 10 d, the light receiving element 31 is arranged atthe first corner, the light emitting element 32 is arranged at thesecond corner, and the RF device element 33 is arranged at the fourthcorner.

FIG. 5B shows an example of a method of placing compound semiconductorchips 36 to manufacture the semiconductor chip 10 shown in FIG. 5A. Asshown in FIG. 5B, in a single chip sharing unit 15, compoundsemiconductor chips 36 are respectively placed: at regions respectivelyincluding the middle parts of a pair of sides; at a region including thecenter; and at the four corners. In this case also, each of the compoundsemiconductor chips 36 is shared by the four chip formation regions 10Rarranged below. In this way, the element patterns of the respective chipformation regions 10R of the chip sharing unit 15, as well as therespective compound semiconductor chips 36, do not need to have thecompletely the same arrangement. Here, each of the compoundsemiconductor chips 36 placed at the regions respectively including themiddle parts of a pair of sides of the chip sharing unit 15 will beprocessed into light receiving elements 31, the compound semiconductorchip 36 placed at the region including the center will be processed intolight emitting elements 32, and each of the compound semiconductor chips36 placed at the corners will be processed into RF device elements 33.Further, in a case where optical function elements of different typesare to be processed, the compound semiconductor layers 37 of thecompound semiconductor chips 36 placed at the respective positions mayhave different constitutions.

In the example shown in FIG. 6A, semiconductor chips 10 e and 10 f oftwo types are included in a semiconductor chip 10. Optical functionelements are respectively arranged at the four corners of each of thesemiconductor chips 10 e and 10 f. Here, the arrangement direction of acertain element pattern is used as a reference, and the upper leftcorner, upper right corner, lower right corner, and lower left corner ofthe semiconductor chip 10 will be referred to as a first corner, secondcorner, third corner, and fourth corner, respectively. In thesemiconductor chip 10 e, a light receiving element 31, which is a firstoptical function element, is arranged at the fourth corner, a lightemitting element 32, which is a second optical function element, isarranged at the third corner, an RF device element 33, which is a thirdoptical function element, is arranged at the first corner, and a sensorelement 34, which is a fourth optical function element, is arranged atthe second corner. In the semiconductor chip 10 f, the light receivingelement 31, which is a first optical function element, is arranged atthe second corner, the light emitting element 32, which is a secondoptical function element, is arranged at the third corner, the RF deviceelement 33, which is a third optical function element, is arranged atthe first corner, and the sensor element 34, which is a fourth opticalfunction element, is arranged at the fourth corner.

FIG. 6B shows an example of a method of placing compound semiconductorchips 36 to manufacture the semiconductor chip 10 shown in FIG. 6A. Asshown in FIG. 6B, in a single chip sharing unit 15, compoundsemiconductor chips 36 are respectively placed: at regions respectivelyincluding the middle parts of a pair of sides; at a region including thecenter; at the four corners; and at regions respectively including themiddle parts of the other pair of sides. In this case also, each of thecompound semiconductor chips 36 is shared by the four chip formationregions 10R arranged below. Here, each of the compound semiconductorchips 36 placed at the regions respectively including the middle partsof a pair of sides of the chip sharing unit 15 will be processed intolight receiving elements 31, the compound semiconductor chip 36 placedat the region including the center will be processed into light emittingelements 32, each of the compound semiconductor chips 36 placed at thecorners will be processed into RF device elements 33, and each of thecompound semiconductor chips 36 placed at the regions respectivelyincluding the middle parts of the other pair of sides will be processedinto sensor elements 34. Further, in a case where optical functionelements of different types are to be processed, the compoundsemiconductor layers 37 of the compound semiconductor chips 36 placed atthe respective positions may have different constitutions.

In the case of FIGS. 4A to 6B also, as described above, no functionblock having a predetermined function is present in a region opposite tothat side where the function block having a large heat release value isarranged with respect to the arrangement position of each of the opticalfunction element 31 to 34.

According to the first embodiment, the optical function element 30 isarranged on the first structure 20 on the substrate 11. The opticalfunction element 30 is arranged such that no function block having apredetermined function is present in a region opposite to that sidewhere the function block having a large heat release value is arrangedwith respect to the arrangement position of the optical function element30. Consequently, it is possible to suppress the thermal influenceapplied to the optical function element 30 from the function blockhaving a large heat release value.

Further, according to the first embodiment, each of the compoundsemiconductor chips 36 is placed at the corner part shared by four chipformation regions 10R adjacent to each other, and then the compoundsemiconductor chip 36 is processed so that optical function elements 30can be respectively included in the chip formation regions 10R. Forexample, as explained in the example described above, it is difficult toplace a compound semiconductor chip 36 having a size of 0.5 mm square orless on the substrate 11 with high precision. However, it is possible toplace a compound semiconductor chip 36 having a size of 1 mm square ormore on the substrate 11 with high precision. Then, the compoundsemiconductor chip 36 thus placed is divided to correspond to adjacentchip formation regions 10R, and thereby each of the optical functionelements 30 derived from the compound semiconductor chip 36 can have asubstantially small size. Accordingly, it is possible to make effectiveuse of the compound semiconductor chip 36, as compared with a case whereone compound semiconductor chip 36 is placed on one chip formationregion 10R.

Further, since one compound semiconductor chip 36 is placed on four chipformation regions 10R, it is possible to improve the productivity aboutplacement of the compound semiconductor chip 36, as compared with a casewhere one compound semiconductor chip 36 is placed on one chip formationregion 10R.

Second Embodiment

In the first embodiment, an explanation has been given to a case where acompound semiconductor chip is placed at the corner part shared by fourchip formation regions adjacent to each other. In the second embodiment,an explanation will be given to a case where a compound semiconductorchip is placed at the side line shared by two chip formation regionsadjacent to each other.

FIGS. 7A and 7B are views schematically showing a structural example ofa semiconductor device according to the second embodiment. FIG. 7A is atop view, and FIG. 7B is a sectional view taken along a line B-B of FIG.7A. This semiconductor device formed of a semiconductor chip 10 has aconfiguration in which a first structure 20, optical function elements30, and second structures 40 are arranged on a substrate 11 having asquare shape, as in the first embodiment.

In the example shown in FIG. 7A, the function blocks arranged here are aprocessor array 211, a peripheral circuit 212, a memory controller 213,an I/O controller 214, a SerDes 215, a reception light/electric signalconversion circuit 216, and an electric signal/transmission lightconversion circuit 217. The reception light/electric signal conversioncircuit 216 and the electric signal/transmission light conversioncircuit 217 are arranged along one side of the square substrate 11.

Further, the optical function elements 30 are bonded on the receptionlight/electric signal conversion circuit 216 and the electricsignal/transmission light conversion circuit 217. Specifically, a lightreceiving element 31 is bonded on the reception light/electric signalconversion circuit 216, and a light emitting element 32 is formed on theelectric signal/transmission light conversion circuit 217. The lightemitting element 32 may be exemplified by a laser diode or the like. Theoptical function element 30 is made of a group III-V compoundsemiconductor, such as InP, GaAs, GaP, or InAs. The optical functionelement 30 is bonded onto the first structure 20 by means of oxide filmbonding or adhesive bonding.

In this respect, in the first embodiment, the optical function element30 is arranged at a corner of the square substrate 11, but, in thesecond embodiment, the optical function element 30 is arranged at aperipheral position of the substrate 11 other than the corners, i.e., itis arranged along a side of the substrate 11. Further, the opticalfunction element 30 is arranged at a position distant from the processorarray 211, which is a function block having a large heat release valuein operation.

In the second embodiment also, the optical function element 30 isarranged such that no function block having a predetermined function ispresent in a region opposite to that side of the arrangement positionwhere the function block having a large heat release value is arrangedwith respect to the arrangement position of the optical function element30, i.e., in a region outside the optical function element 30. In otherwords, no function block is arranged between the optical functionelement 30 and the side closest to the optical function element 30.However, a device element, such as a wiring line, which does not haveits own function may be arranged between the optical function element 30and the side closest to the optical function element 30. The constituentelements corresponding to those of the first embodiment are denoted bythe same reference symbols, and their description will be omitted.

Next, an explanation will be given of a method of manufacturing asemiconductor device having such a structure. FIGS. 8A and 8B are topviews showing part of the sequence of a method of manufacturing asemiconductor device according to the second embodiment. This method ofmanufacturing a semiconductor device is similar to that described in thefirst embodiment. However, when element patterns are formed, two chipformation regions 10R sharing one side line are treated as one chipsharing unit 15 to form element patterns, as shown in FIG. 8A.

In the single chip sharing unit 15, the chip formation regions 10R arearranged to be two-fold rotational symmetric. Specifically, the elementpattern arrangements of the respective chip formation regions 10Rrotated by 180° about the center of the chip sharing unit 15 overlapwith the element pattern arrangements of the respective chip formationregions 10R not rotated.

As shown in FIG. 8A, an X-axis and a Y-axis are defined on the substrate11. It is assumed that, in the single chip sharing unit 15, the regionarranged on the X-axis negative side is a first chip formation region10R-1, and the region arranged on the X-axis positive side is a secondchip formation region 10R-2. On this assumption, the first chipformation region 10R-1 is the same as the second chip formation region10R-2 rotated by 180°.

In order to form the element patterns in a layer of these chip formationregions 10R, a mask (reticle) of only one type is required. In thiscase, when a light exposure process is performed, the mask or substrate11 is rotated accordingly. Alternatively, masks of two types may beprepared such that they have patterns the same in shape and different inorientation by 180°, or a mask of one type may be prepared such that itcan be used to perform light exposure to the entire single chip sharingunit 15 at a time.

When the compound semiconductor chips 36 are bonded onto the substrate11, each of the chips 36 is bonded at or near the middle of the sharedside line in each of the chip sharing units 15, as shown in FIG. 8B.Consequently, one compound semiconductor chip 36 is shared by the twochip formation regions 10R-1 and 10R-2. In this respect, as comparedwith a case where a compound semiconductor chip 36 having a size of, forexample, 0.5 mm square or less is positioned and placed onto each of thechip formation regions 10R, a compound semiconductor chip 36 having asize of 1 mm square can be placed at a predetermined position with highprecision. Further, after one compound semiconductor chip 36 is placedat a position straddling the chip formation regions 10R, the compoundsemiconductor chip 36 is divided to correspond to the respective chipformation regions 10R, and thereby it is possible to make effective useof the compound semiconductor chip 36.

Here, the other steps of the manufacturing method are the same as thosedescribed in the first embodiment, and so their description will beomitted.

According to the second embodiment, there is provided an effect the sameas that explained in the first embodiment. Further, in the secondembodiment, when element patterns are formed onto the substrate 11, theelement patterns need to be formed only in two directions. Accordingly,as compared with the first embodiment in which the element patterns needto be formed in four directions, it is possible to suppressdeterioration of the throughput in manufacturing the semiconductordevice.

In the explanation described above, the optical function elements 30 arebonded onto the first structures 20 on the substrate 11, but the bondingobject is not limited to the optical function elements 30. As thebonding object, a group III-V compound semiconductor element, such as aultra high speed transistor element configured to operate at a frequencynear terahertz, a sensor element, or an actuator element, which is madeof a group III-V compound semiconductor, may be used. Further, in theexplanation described above, a case where the first structures 20includes the reception light/electric signal conversion circuit 207 and216, and the electric signal/transmission light conversion circuit 208and 217 and the optical function element 30 includes the light receivingelement 31 and the light emitting element 32 has been described.However, the first structure 20 may include only the receptionlight/electric signal conversion circuit 207 and 216 and the opticalfunction element 30 may include only the light receiving element 31, orthe first structure 20 may include only the electric signal/transmissionlight conversion circuit 208 and 217 and the optical function element 30may include only the light emitting element 32.

Further, in the explanation described above, the semiconductor chip 10,the chip formation region 10R, and the compound semiconductor chip 36are exemplified with a square shape, but they may have a rectangularshape or another shape.

[Note 1]

A method of manufacturing a semiconductor device, the method comprising:

bonding a compound semiconductor layer to a position straddling aplurality of chip formation regions arranged on a substrate, one of thechip formation regions having a first size, the compound semiconductorlayer having a second size smaller than the first size;

processing the compound semiconductor layer to provide compoundsemiconductor elements on the chip formation regions; and

dividing the substrate to correspond to the chip formation regions.

[Note 2]

The method of manufacturing a semiconductor device according to note 1,wherein the substrate is formed of a silicon substrate.

[Note 3]

The method of manufacturing a semiconductor device according to note 1,wherein an element pattern is formed on one of the chip formationregions having the first size on the substrate.

[Note 4]

The method of manufacturing a semiconductor device according to note 1,wherein

the chip formation region has a rectangular shape, and

in the bonding of the compound semiconductor layer, a first compoundsemiconductor layer is bonded to a region including a center of a chipsharing unit, the chip sharing unit being composed of four chipformation regions.

[Note 5]

The method of manufacturing a semiconductor device according to note 4,wherein, in the bonding of the compound semiconductor layer, secondcompound semiconductor layers are further bonded to four corners of thechip sharing unit.

[Note 6]

The method of manufacturing a semiconductor device according to note 5,wherein, in the bonding of the compound semiconductor layer, thirdcompound semiconductor layers are further bonded to regions includingmiddle parts of a pair of opposite sides of the chip sharing unit.

[Note 7]

The method of manufacturing a semiconductor device according to note 6,wherein, in the bonding of the compound semiconductor layer, the chipsharing unit is composed of the chip formation regions of four typesthat have different element patterns.

[Note 8]

The method of manufacturing a semiconductor device according to note 6,wherein, in the bonding of the compound semiconductor layer, fourthcompound semiconductor layers are further bonded to regions includingmiddle parts of a pair of other opposite sides of the chip sharing unit.

[Note 9]

The method of manufacturing a semiconductor device according to note 8,wherein, in the bonding of the compound semiconductor layer,

the chip sharing unit is composed of the chip formation regions of twotypes that have different element patterns, and

the chip formation regions are arranged such that the chip sharing unitis two-fold rotational symmetric.

[Note 10]

The method of manufacturing a semiconductor device according to note 1,wherein

the chip formation region has a rectangular shape, and in the bonding ofthe compound semiconductor layer, the compound semiconductor layer isplaced at a region including a center of a chip sharing unit, the chipsharing unit being composed of two chip formation regions.

[Note 11]

The method of manufacturing a semiconductor device according to note 10,wherein,

in the bonding of the compound semiconductor layer,

-   -   the chip sharing unit is composed of the chip formation regions        of one type, and    -   the chip formation regions are arranged such that the chip        sharing unit is two-fold rotational symmetric.

[Note 12]

The method of manufacturing a semiconductor device according to note 1,wherein, in the bonding of the compound semiconductor layer, thesubstrate formed with an element pattern and the compound semiconductorlayer are boned to one another via an adhesive.

[Note 13]

The method of manufacturing a semiconductor device according to note 1,wherein the bonding of the compound semiconductor layer includes

planarizing an uppermost surface of the substrate,

terminating a planarized surface of the substrate and a surface of thecompound semiconductor layer with a hydroxyl group,

temporarily bonding the compound semiconductor layer to the planarizedsurface of the substrate, and

finally bonding the substrate and the compound semiconductor layer toone another by heating.

[Note 14]

The method of manufacturing a semiconductor device according to note 1,wherein, in the bonding of the compound semiconductor layer, a compoundsemiconductor chip including the compound semiconductor layer formed ona compound semiconductor substrate is bonded to the chip formationregions.

[Note 15]

A semiconductor device comprising:

a substrate;

a first structure arranged on the substrate, the first structureincluding a function block that includes an element pattern and has apredetermined function; and

a compound semiconductor element directly bonded to the first structure,

wherein no other function block is arranged outside an arrangementposition of the compound semiconductor element.

[Note 16]

The semiconductor device according to note 15, wherein

the substrate has a rectangular shape, and

the compound semiconductor element is arranged at a position mostdistant from a center of the substrate.

[Note 17]

The semiconductor device according to note 15, wherein a plurality ofcompound semiconductor elements are arranged at the first structure.

[Note 18]

The semiconductor device according to note 15, wherein

the first structure includes at least one of a reception light/electricsignal conversion circuit and an electric signal/transmission lightconversion circuit as the function block, and

the compound semiconductor element includes at least one of a lightreceiving element and a light emitting element, the light receivingelement being bonded to the reception light/electric signal conversioncircuit in the case where the first structure includes the receptionlight/electric signal conversion circuit, the light emitting elementbeing bonded to the electric signal/transmission light conversioncircuit in the case where the first structure includes the electricsignal/transmission light conversion circuit.

[Note 19]

The semiconductor device according to note 15, wherein the substrate isformed of a silicon substrate.

While certain embodiments have been described, these embodiments havebeen presented by way of example only, and are not intended to limit thescope of the inventions. Indeed, the novel embodiments described hereinmay be embodied in a variety of other forms; furthermore, variousomissions, substitutions and changes in the form of the embodimentsdescribed herein may be made without departing from the spirit of theinventions. The accompanying claims and their equivalents are intendedto cover such forms or modifications as would fall within the scope andspirit of the inventions.

What is claimed is:
 1. A semiconductor device comprising: a substrate; afirst structure arranged on the substrate, the first structure includinga function block that includes an element pattern and has apredetermined function; and a compound semiconductor element directlybonded to the first structure, wherein no other function block isarranged outside an arrangement position of the compound semiconductorelement, when a center side of the substrate is an inside and aperiphery thereof is an outside.
 2. The semiconductor device accordingto claim 1, wherein the substrate has a rectangular shape, and thecompound semiconductor element is arranged at a position most distantfrom a center of the substrate.
 3. The semiconductor device according toclaim 1, wherein a plurality of compound semiconductor elements arearranged at the first structure.
 4. The semiconductor device accordingto claim 1, wherein the first structure includes at least one of areception light/electric signal conversion circuit and an electricsignal/transmission light conversion circuit as the function block, andthe compound semiconductor element includes at least one of a lightreceiving element and a light emitting element, the light receivingelement being bonded to the reception light/electric signal conversioncircuit in the case where the first structure includes the receptionlight/electric signal conversion circuit, the light emitting elementbeing bonded to the electric signal/transmission light conversioncircuit in the case where the first structure includes the electricsignal/transmission light conversion circuit.
 5. The semiconductordevice according to claim 1, wherein the substrate is formed of asilicon substrate.
 6. The semiconductor device according to claim 1,further comprising a second structure that is arranged on the firststructure provided with the compound semiconductor element.
 7. Thesemiconductor device according to claim 6, wherein the second structureis a wiring structure that connects the compound semiconductor elementto another device element built in the first structure.
 8. Thesemiconductor device according to claim 1, wherein the compoundsemiconductor element is bonded onto the first structure by means ofoxide film bonding or adhesive bonding.
 9. The semiconductor deviceaccording to claim 1, wherein the substrate has a rectangular shape, andthe compound semiconductor element is arranged at a first corner of thesubstrate.
 10. The semiconductor device according to claim 9, whereinthe first structure includes a processor as the function block, and theprocessor is arranged at a position distant from the first corner. 11.The semiconductor device according to claim 10, wherein the otherfunction block is arranged between the compound semiconductor elementand the processor.
 12. The semiconductor device according to claim 3,wherein the substrate has a rectangular shape, and the compoundsemiconductor elements are arranged at a first corner and a secondcorner of the substrate.
 13. The semiconductor device according to claim12, wherein the second corner exists at a diagonal of the first corner.14. The semiconductor device according to claim 3, wherein the substratehas a rectangular shape, and the compound semiconductor elements arearranged at a first corner, a second corner and a third corner of thesubstrate.
 15. The semiconductor device according to claim 3, whereinthe substrate has a rectangular shape, and the compound semiconductorelements are arranged at four corners of the substrate.
 16. Thesemiconductor device according to claim 1, wherein the substrate has arectangular shape, and the compound semiconductor element is arranged ata peripheral position of the substrate other than the corners.
 17. Thesemiconductor device according to claim 16, wherein the compoundsemiconductor element is arranged along a first side of the substrate.18. The semiconductor device according to claim 17, wherein anotherfunction block is not arranged between the compound semiconductorelement and the first side.
 19. The semiconductor device according toclaim 17, wherein the first structure includes a processor as thefunction block, and the processor is arranged along a second sideopposed to the first side.
 20. The semiconductor device according toclaim 19, wherein the other function block is arranged between thecompound semiconductor element and the processor.